A more CMOS process compatible scheme to tune the Schottky Barrier Height of NiSi to electrons by means of dopant segregation (DS) technique

In this paper, a more CMOS process compatible scheme to tune the Schottky Barrier Height (SBH) of NiSi to electrons (φ
_bn
) by means of boron (B) dopant segregation (DS) technique is presented. This scheme consists of the following steps: (1) deposit Ni layers on Si substrate; (2) rapid thermal anneal (RTA1) at 300°C/60 s to form Ni-rich silicide followed by un-reacted Ni strip; (3) implant B ions into preformed Ni-rich silicide; (4) RTA2 at 450-700 °C/30 s to transform Ni-rich silicide to NiSi and to induce B DS at NiSi/Si interface as well. The φ
_bn
tuned using this scheme by B DS is ≥ 1.0 eV, identical to that tuned using conventional scheme by B DS, in which B ions are implanted into NiSi followed by drive-in annealing to induce B DS at NiSi/Si interface.