A proposed high manufacturability strain technology for high-k/metal gate SiGe channel UTBB CMOSFET

We demonstrated a high-k/metal gate-last SiGe channel ultra ultra thin body and BOX (UTBB) CMOSFET process with optimized strain technology for high performance concerns. The impact of SOI thickness and strain from Ge, CESL, and high-k material/metal-gate are inspected. An appropriate post treatment is proposed to improve quality of stack Hf-based dielectric. We achieved a high manufacturability 28nm SiGe channel UTBB Hf-based high-k/TiN-based metal-gate last CMOSFET with good V
_T
roll-off, lower device leakage and better reliability.