A shuffle frog-leaping algorithm for test scheduling of 2D/3D SoC

Test scheduling is an important issue for testing the SoC. This work proposes a modified shuffle frog-leaping algorithm for test scheduling to reduce the test application time under the peak power constraint. It is applied to the 2D as well as the 3D SoC and experimental results on benchmark circuits show that it is one of the most effective algorithms in solving the problem.