Low cost VLSI design of the LDPC decoder in Advanced Broadcasting System for Satellite

In this paper, a low cost VLSI implementation of an LDPC decoder for the Advanced Broadcasting System of Satellite (ABS-S) is presented. The decoder is fully compatible with all the 8 code rates in ABS-S standard. The layered decoding with sorted scheduling architecture is employed and the scaled min-sum belief propagation method is used for check node update. The CRC check is embedded into the decoding process to gain the best early stopping effect in decoding iterations. The decoder is implemented in Altera FPGA and results show that the proposed decoder is suitable for satellite broadcasting application ABS-S and its scheme can be generalized in other quasi-cyclic structured LDPC codes.