Electrostatic discharge (ESD) and latchup in 3-D memory and system on chip applications

Electrostatic discharge (ESD) protection and latchup issues in three dimensional (3-D) semiconductor chip systems is discussed for the first time. ESD protection in 3-D multi-chip systems will be important for both memory and system-on-chip (SOC) applications. Two types of 3-D semiconductor chips will be discussed; a first version introduces edge wiring, and a second version introduces through silicon vias (TSV). In this paper, a new memory device built using the first commercial CMOS manufacturing technology to employ TSVs will be discussed.