A 25–28Gbps clock and data recovery system with embedded equalization in 65-nm CMOS

A novel CDR system with a built-in equalizer for compensating electrical/optical channel loss is presented. A variable-gain delay line is implemented to perform both data delay and equalization simultaneously without consuming extra power. Designed in a 65-nm 1P9M general-purpose CMOS process, the proposed CDR system employs current-mode logic circuits extensively with shunt peaking inductive load to attain the required gain at high speed. To minimize the area occupied by the spiral inductors, custom stacked inductors, achieving an inductance density of 0.3pH/um
²
, are used. The prototype IC occupies less than 0.9mm
²
. Post-layout simulation results show that the CDR is able to recover a 28-Gbps NRZ PRBS data after transmission through a channel with 10-dB loss at 14 GHz when the equalization function is activated. The CDR consumes 100mA from a 1-V supply.