A generic FPGA emulation framework

Verification techniques face growing challenges, as digital system design becomes increasingly complex. Currently, verification is believed to be the main bottleneck for expedite complex designs, consuming at least 70% of the whole system development effort. This paper proposes a new, generic hardware emulation framework to improve the observability of designs as well as reducing emulation-based verification intrusiveness. The proposed emulator provides enhanced observability and controllability of inner workings of the system when compared to commercial FPGA-based emulators and is less intrusive on the design under verification. As FPGA-vendor specific products, the proposed emulator is generic, supporting in principle any digital system design. To enhance flexibility, stimuli generation and response capture is under control of a host computer and communication between the host and the design under verification may occur through an Ethernet interface or through PCIe interfaces in supported platforms. The prototype of the proposed framework is operational and presents promising results in terms of observability and controllability enhancement, although further work is needed to improve the framework emulation performance.