A double-delta compensating technique for pulse-frequency modulation CMOS image sensor

We design a double-delta compensating (DDC) technique for a comparator-based pulse-frequency modulation (PFM) pixel. This technique has been demonstrated by simulation to achieve both fixed-pattern noise (FPN) reduction and dynamic range (DR) extension at the high-light region. According to the result, the pixel DR extends by at least 12 dB; FPN is reduced from unacceptable levels to 1-3% when it is caused by the comparator offset voltage or less than 3.5% when the layout and process variations are considered. These simulations have been performed using the Monte Carlo method for realistic parameter variations in a 0.18-μm CMOS technology.