Roundoff noise analysis of state-space digital filters implemented on floating-point digital signal processors

An expression is obtained for the output floating-point roundoff noise variance of a general Nth-order state-space digital filter with zero-mean white noise input signal. This expression is then simplified for the case there the filter is implemented on a floating-point digital signal processor. Such processors carry extended precision bits in the accumulation register, so that the primary source of roundoff error in the output arises from the final quantization of the mantissa. Under this condition of extended precision during multiply-accumulate, it is found that the floating-point roundoff noise gain is identical to the fixed-point roundoff noise gain used extensively in the past for designing optimal and near-optimal fixed-point digital filters. Therefore, previous work to optimize fixed-point realizations is directly applicable to the floating-point realizations. This conclusion is verified by actual roundoff noise measurements using a digital signal processor simulator. Since floating-point digital filters do not require scaling, optimal floating-point realizations require N fewer multiplies than fixed-point filters. Simple design equations are presented for the floating-point minimum-noise second-order state-space structure with two trivial unity multiplies.