A mathematical basis for power-reduction in digital VLSI systems

Presented in this paper is a mathematical basis for power-reduction in VLSI systems. This basis is employed to: (1) derive lower bounds on the power dissipation in digital systems; and (2) unify existing power-reduction techniques under a common framework. The proposed basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement of R bits/s. Architectures implementing a given algorithm are equivalent to communication networks each with a certain capacity C (also in bits/s). The absolute lower bound on the power dissipation for any given architecture is then obtained by minimizing the signal power such that its channel capacity C is equal to the desired information transfer rate R. By including various implementation constraints, increasingly realistic lower bounds are calculated. The usefulness of the proposed theory is demonstrated via numerical calculations of lower bounds on power dissipation for simple static CMOS circuits. Furthermore, a common basis for some of the known power-reduction techniques such as parallel processing, pipelining and adiabatic logic is also provided.