An Address-Based Compiling Optimization for FFT on Multi-cluster DSP

This paper presents a compiling optimization for FFT program on multi-cluster DSP based on analysis of memory address. We transform the loops in order to reduce the number of instructions in the innermost loop. The interrelationship between each two memory access operations can be acquired via analysis of the base address and offset of every load or store instruction in the basic block. After the process of forward and backward scanning following the data-flow graph, we insert intercluster move instructions and merge several instructions into one SIMD operation. The experimental result shows that the FFT program compiled by the compiler using our optimization method achieves 13.57 times performance improvement on average than the unoptimized program.