Analytical study of the effect of asymmetric gate bias on the performance of double gate TFET

In this paper we have investigated the effect of asymmetric gate bias on the performance of a double gated TFET structure. We have carried out an extensive simulation study on a recently reported novel electron hole bilayer TFET structure. The structure exhibits a high on current in the range of 50 μA/μm and the off current remains as low as 10
^-15
Ampere/μm. So a I
_on
/I
_off
ratio of 10P
¹⁰
can be achieved. Subthreshold swing has also been reduced to a value of 18mV/decade. The device principle and performance are investigated by 2D numerical simulation.