An investigation in the impact of structural parameters on the electrical characteristics of Nanoscale Heterostructure P-MOSFETs

Over the past few decades, CMOS has proved to be the choice device in the fabrication of the high density integrated circuits. However, in this technology the device performance is degraded primarily due to mobility limitation in PMOSFET. One way to elevate this problem is to alter electronic properties of the channel region using strained layers. In this paper, we propose a novel Heterosructure PMOSFETs with optimum Ge content in SiGe layer. This investigation proves that an increase in Ge mole fraction reduces threshold voltage on Si/SiGe interface, while threshold voltage on Si/SiO
₂
is increased. As the Ge mole fraction is increased the gate capacitance also will increase. The results provide useful guide lines for optimizing Nanoscale Heterostructure for low power applications.