Physical layer implementation of orthogonal frequency division multiplexing for software defined radio on FPGA

This paper discusses the implementation of a software defined radio (SDR) that uses orthogonal frequency division multiplexing (OFDM). The transmitter and receiver were modeled and simulated using the Xilinx
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blockset in MATLAB Simulink
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then implemented on hardware using Xilinx
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System Generator. Performance of the SDR system was evaluated by measuring BER, PAPR and spectral efficiency under simulated channel conditions with SNR of 15 and 20 dB. For speech inputs, 8-FFT 16ASK and 16-FFT 64ASK are acceptable for SNR of 15 and 20 dB, respectively. For audio inputs, 8-FFT PSK and 8-FFT 16ASK are acceptable. These were based on a minimum BER of 10-2 for speech and 10-3 for audio inputs. The chosen configurations were implemented on a Xilinx
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Virtex-5 FPGA built in the XtremeDSP™ Development Platform ML506 Edition using JTAG hardware co-simulation. The BER performance of the system on hardware was consistent with that observed in simulations using fixed-point computations.