RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer

As CMOS technology continues to scale down, allowing operation in the GHz range, it provides the opportunity of low cost integration of analog, digital and RF functions on the same wafer for System-on-Chip (SoC) applications [1]. SoC circuits on Si are prone to substrate losses and coupling, especially when RF analog and digital functions are integrated together into the same chip. In digital circuits, substrate coupling can also cause fluctuations in the propagation delay of logic gates by changing the threshold voltage of devices through the body effect [2]. The development of SOI technology presents the major advantage of providing high resistivity silicon (HR-Si) substrate capabilities, which are mandatory for highperformance RF integrated circuits [3], leading to substantially reduced substrate RF losses and crosstalk [4]. However, oxidized HR-Si wafers suffer from parasitic surface conduction (PSC) due to fixed charges (Q
ox
) within the oxide which attract free carriers near the Si/SiO
2
interface, hence reducing the substrate effective resistivity (ρ
eff
) and increasing substrate losses [5]. In addition, PSC increases the non-linearities originating from the substrate [6] and RF devices are more sensitive to variations of the DC voltage [7]. Several techniques have been developed to reduce these parasitic effects and to enhance the HR properties of Si material. The introduction of a trap-rich layer has been proved as the most effective technique while being compatible with industrial SOI wafer fabrication and with the important thermal budget of standard CMOS process [5]. The traps capture the free carriers at the Si/SiO
2
interface, thereby enabling the substrate to recover its nominal resistivity [5], linearity, eliminating the DC dependency [6], [7], and leading to a substantial reduction of RF losses and crosstalk [8].