Ground plane optimization for 20nm FDSOI transistors with thin Buried Oxide

Planar fully depleted (FD) devices with thin Buried Oxide (BOX) offer the unique ability to incorporate effective back biasing which is a key enabler to build a versatile multi-Vt technology. From a dynamic standpoint, forward back bias lowers Vt and thus boost device performance, whereas reverse back bias increases Vt and thus decreases leakage. From a static point of view the back gate allows fine Vt tuning. Here we propose and evaluate a back gate implant scheme that enables a full use of the back bias.