H.264/AVC motion estimation on FPGAs and GPUs: A comparative study

Video compression has been receiving much deserved attention due to the widespread adoption of digital video technology, and the need of optimizing the storage and transmission of such media. In this paper, we are concerned with the optimization of one step of the H.264 compression standard, namely, the motion estimation, in which motion vectors coding the movement of macroblocks (or sub-macroblocks) between two frames are computed. Specifically, we present here a comparative study between two architectures that were used to implement the full search (FS) algorithm for single pixel precision according to the standard H.264/AVC. We are particularly concerned with the relation area × throughput of the two architectures. We report here on experiments performed on CIF, SD and full HD data, comparing the maximum throughput achieved and bandwidth required by the architectures.