Silicon-Embedding Approaches to 3-D Toroidal Inductor Fabrication

This paper presents complementary-metal–oxide–semiconductor-compatible silicon-embedding techniques for on-chip integration of microelectromechanical-system devices with 3-D complex structures. By taking advantage of the “dead volume” within the bulk of the silicon wafer, functional devices with large profile can be embedded into the substrate without consuming valuable die area on the wafer surface or increasing the packaging complexity. Furthermore, through-wafer interconnects can be implemented to connect the device to the circuitry on the wafer surface. The key challenge of embedding structures within the wafer volume is processing inside deep trenches. To achieve this goal in an area-efficient manner, straight-sidewall trenches are desired, adding additional difficulty to the embedding process. Two approaches to achieve this goal are presented in this paper, i.e., a lithography-based process and a shadow-mask-based process. The lithography-based process utilizes a spray-coating technique and proximity lithography in combination with thick epoxy processing and laminated dry-film lithography. The shadow-mask-based process employs a specially designed 3-D silicon shadow mask to enable simultaneous metal patterning on both the vertical sidewall and the bottom surface of the trench during deposition, eliminating multiple lithography steps and reducing the process time. Both techniques have been demonstrated through the embedding of the topologically complex 3-D toroidal inductors into the silicon substrate for power supply on-chip (PwrSoC) applications. Embedded 3-D inductors that possess 25 turns and a diameter of 6 mm in a silicon trench of 300-
$\mu \hbox{m}$
depth achieve overall inductances of 45–60 nH, dc resistances of 290–400
$\hbox{m}\Omega$
, and quality factors of 16–17.5 at 40–70 MHz.
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[2012-0187]