Performance of router design for Network-on-Chip implementation

In this dissertation work, router has been designed for providing high throughput by overcoming disadvantages of switch. The router provides high speed dynamic arbitration compared to traditional switches and makes it fair at the cost of extra energy consumption. This work mainly includes the performance evaluation of mesh based interconnection networks under self-similar traffic condition. Network on Chip (NoC) is emerging as an efficient communication backbone for next generation Multi-Processor System on Chip (MPSoC). The NoC architecture is data packet based communication network on a single chip. The NoC architecture is m*n mesh of switches & resources are placed on the slots formed by switches. Recourses can be processor core a DSP core, an FPGA block, memory block of any kind such as RAM, ROM or any other intellectual property block. The resources are connected by the Interconnect IPs. The main component of IIP is network interface and the switch. Each switch is connected to the one recourses and our neighboring to the one resources and each resource is concept of region which occupies an area of any number o resources and switches.