Hardware implementation of PAPR reduction scheme for OFDM system

High Peak to Average Power Ratio (PAPR) is one of the major challenges of any Orthogonal Frequency Division Multiplexing (OFDM) system. Many methods have been suggested for reducing PAPR. In this paper we design and implement an OFDM system on a FPGA along with PAPR reduction using Selected Mapping (SLM) technique. We analyse challenges in practical implementation of the system and also investigate the resource utilization increase as compared to a normal OFDM system.