A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues

We discuss dynamic read and write stabilities of embedded SRAMs in 28-nm high-k/metal-gate (HK/MG) bulk CMOS technology. Test chips which include 1-Mbit single-port SRAM and 512-kbit dual-port SRAM macros are designed and fabricated. A Good correlation for minimum operating voltage (V
_min
) between simulation and measurement is observed. We also introduce the test screening circuitry which takes the dynamic stability into consideration. We obtain the appropriate screening results from the evaluations of the testchip. It is also confirmed assured screening with 2.0% dynamic stability fault detection for an SoC product.