Behavioral synthesis of testable systems with VHDL

A methodology for automatically synthesizing a testable RTL (register-transfer-level) hardware specification from a behavioral VHDL (VHSIC hardware description language) specification is presented. Behavioral synthesis is described. It consists of the automatic creation of a hardware specification, given an input specification that describes how the hardware operates in response to its current state and the states of its input signals. The synthesis methodology includes techniques for ensuring that the resulting hardware is testable. The techniques used for mapping the input behavioral model to hardware assume that the resulting hardware is fully synchronous and serial scan compatible. The synthesis process recognizes expressions and operations in the behavioral model and maps them to corresponding hardware components that are included in a separate VHDL library.<
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