Innovative Barrier CMP Process: Benefit of High Selective Approach on Morphological and Electrical Performances

Copper line interconnections in back end of line (BEOL) field is controlled by chemical mechanical polishing (CMP) processes. Indeed, after ultra low k (ULK) deposition, Cu lines are patterned using Trench First Hard Mask (TFHM) architecture. Damascene approach allows to planarize and remove the excess of Cu, barrier and metal hard-mask. Standard direct CMP barrier leads to TEOS removal landing on ULK layer. Such process provides a large gain in capacitance (no contribution of dense dielectric SiOCH) while the porous ULK integrity is maintained. However, since several CMOS technologies nodes, dielectric constant (k) decreases until 2.5 at 32nm node (porosity > 30%). Such a CMP process is particularly challenging and requiring optimized selectivity for the each layer involved (barrier metal, Cu, Oxide, ULK, etc). Moreover a stringent defect requirement, compatible with fragile and porous characteristic of the ULK layer without k-shift degradation, is mandatory. For 32nm technologies nodes, high selective slurry was investigated between the Hard Mask (HM SiO2) and SiOCH layer, on topography and electrical performances. This new complementary study exercises the new selective approach through electrical patterned wafers. The generated results confirm a huge time process window and a clear thickness uniformity improvement, which allow directly a better distribution and therefore a tighter control of the resistance & capacitance product. Finally, this process characterization opens a path to a new BEOL architecture to find out the better tradeoff between CMP process control and pattern dimensions. Keywords: ICPT 2012, CMP, Barrier slurry, High selectivity, Topography, Electrical performances