0.18μm CMOS limiting amplifier for 10Gb/s optical receiver

We realized 10Gb/s limiting amplifier by using SMIC 0.18μm 1P6M mixed-signal CMOS process. Without any inductors, the bandwidth of the amplifier is effectively increased while maintaining a flat frequency response by using a third-order interleaving active feedback. The post-simulation results indicates that it can work at the bit-rate of 10Gb/s, a small-signal gain is 45.6 dB, a −3-dB bandwidth is 8.9 GHz, and an input sensitivity is 5mV at 10Gb/s data-rate. It can achieve an output swing of 400mV with 50Ω external load resistors. The circuit consumes a DC power of 163mW from a 1.8V supply voltage. The active area is μm ×600μm.