Logical effort of CNFET-based circuits in the presence of metallic tubes

CNFETs have potentials of becoming successors to CMOS devices. In this paper we explore value of the logical effort technique to design robust CNFET-based circuits that due to the presence of unwanted metallic tubes and variations of device parameters behave as stochastic systems. The presence of metallic tubes is one of the major fabrication challenges as it negatively impacts the performance, power and yield of CNFET-based circuits. We developed capacitance-based logical effort models to estimate the delay of CNFET-based circuits in the presence of metallic tubes, and when the metallic tubes are removed by one of known processing techniques. Our Monte Carle simulation uses the developed logical effort models to evaluate delay and functional yield of various types of stochastic logic gates and bigger building blocks. The simulations were done for fanout of one (FO1) and fanout of four (FO4) inverter chain, NAND gate, and 4-stage decoder circuit. The variation in the metallic tube presence was varied from 0% to 20%. The logical effort technique shows high potential for being very efficient in evaluation and optimization of stochastic CNFET-based designs.