A novel architecture for binary comparison using time division de-multiplexing technique

This paper proposes the design of a novel comparator which uses a Time Division De-multiplexing (TDD) unit for binary comparison. The function of the TDD unit is to generate clock pulses in such a pattern that they can be used to trigger one of the two D flip-flops in the proposed comparator architecture, depending on - which of the two numbers being compared is greater. The proposed comparator is simulated using Verilog HDL programming in Xilinx ISE 8.2i platform and its functionality is verified. An application-specific advantage of this architecture is proposed in this paper.