Multiplier-less based architecture for variable-length FFT hardware implementation

This paper presents a new variable-length, multiplierless Fast Fourier Transform (FFT) hardware implementation. The proposed implementation handles with 16, 64 and 128 point FFT frames. The architecture is designed based on Single-path Delay Feedback (SDF) scheme which implements the mixed radi×2, 2
²
FFT algorithms. In order to improve the performance, the complex multipliers are replaced by simpler and faster units which use only shift and addition/subtraction operations. As consequence, we obtain twofold increase in the speed.