Implementation of Fractal image compression on FPGA

Fractal Image Compression (FIC) is known as a lossy technique, which requires a large amount of operations to complete the codification. The development of VLSI technology allows the creation of complete systems inside a single chip likely FPGA, therefore the number of required operations may reduce and data compression becomes increasingly significant for storage and transmission. In this paper, we propose the implementation of a FIC framework on Xilinx Virtex 5 (XUPV5-LX110T) FPGA board, which allows to significantly decrease the elapsing time compared to that implemented in DSP at the same clock rate of 100MHz. The experimental results performed by Fisher's method for a gray level image have verified the possibility to design a SoC for fast fractal coder/decoder with an increased compression performance.