A low-power 18-GHz dual-injection-locked frequency divider in 65-nm CMOS

In this paper, an 18-GHz dual-injection locked frequency divider (ILFD) is presented. In order to decrease the complexity of PLL design, the dual-ILFD doesn't adopt a frequency adjustment scheme but achieves a large locking range due to fully utilizing the voltage and current injection of the input signal. This ILFD is implemented in SMIC 65nm CMOS technology and consumes 1.8mW from a 1.2V voltage supply excluding buffers and biasing circuits. The core area is 0.35mm× 0.73mm. The measured locking range is 13.3GHz~18.4GHz with 0dBm input power.