Clock Skew Optimization in Pre and Post CTS

The clock distribution is important in all synchronous VLSI Design. The clock skew impacts the performance of synchronous logic circuits. As the scaling moves to nanometer technology, innovative clocking techniques are required to optimize the skew. This is done in backend process of design flow, (i.e.) skew is optimized in Pre and Post CTS. Here tunable clock buffers and tunable clock inverters is designed and it is compared. These designed buffers and inverters are useful for clock skew optimization in pre and post CTS.