Reliability estimation for time redundant error correcting adders and multipliers

There has been much study of concurrent error correction in arithmetic processors like adders and multipliers but they are not practical because of their high expense. The redundancy introduced to achieve fault-tolerance in a system can be in the form of either hardware, information, or time. The most straightforward method is to use hardware redundancy by triplicating the adder or multiplier and taking a majority vote at the output. This is called Triple Modular Redundancy (TMR). The concept is simple but the hardware overhead is high. With the information redundancy approach, error correcting codes are used but the complexity is prohibitively high. Time redundancy is an approach to achieve fault-tolerance for arithmetic processors without introducing too much hardware overhead. It can be used in applications where minimizing the hardware complexity is the primary concern. REcomputing with Triplication With Voting (RETWV) is an error-correcting architecture using time redundancy. It is practical because its hardware overhead is much lower than that of the other approaches and their delay time is acceptable. In this paper, the reliability of VLSI time redundant error-correcting adders and multipliers is estimated. It is shown that RETWV has higher reliability improvement than that obtainable by TMR.