Design of cover circuits for monitoring the output of a MISA

In this paper, an improved BIST structure is investigated. The output of the MISA is monitored by an error detection circuit during the application of the test sequence. The error detection circuit has to detect only those faults which are aliased by the MISA. By use of this method, no erroneous output sequence of the circuit under test can go undetected. It is demonstrated how the error detection circuit can be realized by two simple cover circuits. Simulation experiments indicate that the hardware overhead for the cover circuits is less than 2% of the circuit under test. It is also demonstrated that in concrete designs the probability of an arbitrary fault-not necessarily in the fault model considered-remaining undetected is significantly smaller than with conventional BIST structure.