Scheduling policies for fault tolerance in a VLSI processor

This paper presents analytical and simulation models for evaluating the operation of a VLSI processor (in a uniprocessor configuration) which utilizes a time-redundant approach (such as recomputation by shifted operands) for fault-tolerant computing. In the proposed approach, all incoming jobs to the uniprocessor are duplicated, thus two versions of each job must be processed. A discrepancy in the results produced by comparing the outcomes of the two versions of the same job indicates that a fault may have occurred. Several methods for appropriately scheduling the primary and secondary versions of the jobs are proposed and analyzed.