Communication Control for Multi-core Processors

A reconfigurable System-on-Chip (SoC) for multimedia application was introduced in this paper, where the SoC consisted of a master processor and slave processor. We individually simulated the master processor with DLX pipeline processor and the slave processor with Xtensa processor that was able to establish a excellent multimedia processor with multi-core than the traditional one. As a result, we get some benefits in area and power, and then the proposed architecture can be configured in multiprocessors architecture.