A robust receiver for power line communications in integrated circuits

This paper presents a power line communications (PLC) receiver in ICs with emphasis on robustness. The PLC receiver intends to control internal logic values of ICs through power pins. It employs a differential Schmitt trigger to increase noise immunity and tolerate supply voltage fluctuations. The receiver is designed and laid out in 0.18 μm CMOS technology. Post-layout simulation results show that the receiver can operate up to 22.2 percent of the supply voltage drop under the signal-to-noise ratio (SNR) of 16.3 dB. The receiver dissipates 2.4 mW under 1.8 V supply, which is lower than earlier PLC receivers.