A video encoder/decoder architecture for consumer-use HD-DVCRs

In this paper, we propose a video encoder/decoder architecture for HD-DVCRs based on the specifications of consumer-use digital VCRs. To reduce hardware complexity a novel quantizing number (QNO) selection algorithm and a flexible memory mapping method are developed. Within a few predicted candidates, one QNO is selected for a segment adaptively using a non-zero symbol counter and a target symbol modification. Each macroblock's QNO is then determined based on the selected segment QNO. The arranging algorithm of a segment is implemented with minimal memory using flexible block mapping. Most of the hardware including memory is shared both in the encoding and decoding process. The proposed architecture is described using Verilog-HDL and its functionality is verified with four types of pictures.