Optimising designs for hardware compilation to FPGAs

Field programmable gate arrays with their re-configurable architectures are a powerful tool for implementing re-configurable computing. Using the facility of re-programmability, designs can be optimised for specific cases and then implemented in hardware, achieving performance improvements over the software design. As the physical architecture itself places size and speed constraints on the designs, we present bit level optimisations and a design and layout tool to improve the benefits achievable with the re-programmability, for regular numerical designs.