VLSI design of DLMS adaptive IIR filters for high speed echo cancellation

In this paper we present a novel VLSI design of adaptive IIR filters for high speed channel echo cancellation. In the algorithm level, the delayed LMS adaptation algorithm is adopted to exploit the computing concurrency between the adaptation and the filtering sections. In addition, the non-recursive equation error criterion is employed to speed up the computation in the adaptation section. In the architecture level, a distributed arithmetic (DA) based inner product computing scheme is devised to achieve the high throughput operation. In the circuit level, a bit serial systolic array circuitry is derived for modular and low complexity design. Performance simulation is conducted first to determine the design spec and the VLSI implementation features a 4000/spl times/3400 um/sup 2/ core design with 100,000 transistors. Post layout simulation result indicates the resultant 4-tap adaptive IIR filter design can reach a processing rate as high as 3.33 M samples per second.