3-D interconnection for ultra-dense multichip modules

A three-dimensional interconnection technology is described that allows a reduction of the occupied area by a factor of 7 or 8 as against 2-D interconnection. The approach consists of interconnecting the bare chips not in the XY plane, but along the Z-axis. The process entails interconnecting the four lateral areas (sides) of the cube formed by stacking n chips (n=8-10) on top of one another. The chips are individually interconnected on a thin film identical to a TAB (tape automatic bonded) film by means of gold wires, prior to cubing. These chips are standard, off-the-shelf, bump-free devices. After passing electrical testing and burn-in, they are then glued on top of one another with the TAB film. After these n chip+film assemblies have been cured (polymerized), a trim operation is carried out to cut the n-chips cube out of the TAB-film carrier cube. The trim line is approximately 100 mu m from the edge of the chips. The cube containing the n chips thus provides four lateral areas (sides) in which appear the cross sections of the gold wires connecting each lead of each chip to the corresponding leads on the flexible films. These gold wire cross-sections may be interconnected in two different ways according to the number of chip layouts/outputs or the conductor pitch.<
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