A performance study of layout and Vt options for low noise amplifier design in 65-nm CMOS

This paper studies the trade-off between different cell-based layout styles and V
_t
options using a set of 5-GHz differential cascode LNAs. The test chip is fabricated in 65-nm CMOS process. The impact of merged diffusion area at the cascode node, the effect of gate contact style as well as the usage of normal V
_t
versus low V
_t
are presented. Our measurement results show that using individual device layout with separated diffusion area, low V
_t
and double-sided gate contact provides better gain and noise performance. Specifically, the power gain and noise figure (NF) are improved by 1.5 dB and 0.3 dB, respectively, under the same bias current and power consumption. On the other hand, using normal V
_t
devices with merged diffusion area achieves significantly better linearity with about 4-dBm increase in IIP3. Based on these findings, recommended layout and V
_t
usage guidelines for RF amplifier design in 65-nm technology are proposed.