Plenary presentation — Keynote I — Goldilocks failures: Not too soft, not too hard

The semiconductor industry continues to push Silicon scaling for the next ten years since no viable alternative technology is sufficiently mature in that time frame. Simultaneously, the delay in crucial technologies like UV complicates further scaling by increasing cost and imposing ever larger tolerances that erode performance and density gains. The increasing levels of variability are creating new types of circuit failures which fall between the traditional "hard" and "soft" categories. This phenomena has been observed for some time in SRAM, but it is now seen in other sensitive circuits like latches. Studying this behavior leads to two important research opportunities: bridging the gap between performance prediction and test, as well as preparing the CAD and Test communities for future post-CMOS technologies.