A variation-aware 0.57-V set-associative cache with mixed associativity using 7T/14T SRAM

In this paper, we present a novel cache scheme which efficiently reduces the minimum operating voltage (V
_min
) despite manufacturing-induced defective SRAM cells. The proposed low-voltage scheme exploits the fact that locations of defective SRAM cells are usually non-uniformly scattered. It also leverages the reliable characteristics of 7T/14T SRAM and allows associativites in each index to be different. Our evaluation results show that the proposed cache can reduce V
_min
of 64 KB 8-way set-associative cache by 80 mV within 7.81% capacity and 5.22% area overhead.