Two-phase flow boiling in a single layer of future high-performance 3D stacked computer chips

The present study focuses on an experimental investigation of two-phase flow boiling in a silicon multi-microchannel evaporator, which emulates a single layer of a 3D stacked computer chip. The micro-evaporator is comprised of 67 parallel channels, each having a 100 × 100 μm
²
cross-section area, and separated by 50 μm-wide fins. Two aluminium micro-heaters were sputtered onto the backside of the test section to provide two 0.5 cm
²
heated areas in order to simulate the power dissipated by active component in 3D CMOS chips. The experiments were performed with a second identical test section having 50 μm-wide, 100 μm-deep, and 100 μm-long restrictions (micro-orifices) at the inlet of each channel to stabilize the two-phase flow. The goal of this experimental campaign was to perform simultaneous high-speed flow visualization and infra-red measurements of the two-phase flow and heat transfer dynamics across the entire micro-evaporator area. Refrigerants R245fa, R236fa and R1234ze(E) were chosen as the working fluids. The micro-orifices successfully suppressed back flow, eliminated flow instabilities, provided a good flow distribution, and started the boiling process with some flashed vapor. Thermal performance was found to be uniform widthwise using these orifices.