A Scalable Low-Voltage Signaling (SLVS) Driver for a Low-Power MIPI M-PHY Serial Link in 40 nm CMOS

This paper presents the design and simulations of a scalable low-voltage signaling (SLVS) type output driver for a MIPI M-PHY serial link. The specified data rate is 5.8 Gb/s at the maximum, which makes particularly the pre-driver design challenging. The link is targeted for battery-powered mobile applications. Therefore, a low power budget is an important issue and makes use of CMOS logic for the pre-driver most attractive. Minimizing the common-mode interferences at the output is crucial for acceptable low electromagnetic coupling from the serial link. In addition to the output driver, two other key blocks are considered. A low-dropout voltage (LDO) regulator provides the supply voltage (200-400 mV) for the driver. A sense amplifierbased flip-flop (SAFF) is utilized as the pre-driver to synchronize the data to be sent. Simulations show correct operation of the output driver and SAFF at 5.80-Gb/s with a low enough commonmode content in the output spectrum, while consuming total power (the LDO, SAFF and driver) of 2.4 mW.