Behavioral model of split capacitor array DAC for use in SAR ADC design

A model of a switched capacitor digital-to-analog converter (DAC) based on a split capacitor array is presented for use during the design of a successive approximation register (SAR) analog-to-digital converter (ADC). The model takes the effects of parasitic capacitors into account, and the values of these parasitic capacitors can be extracted from the circuit topology by using Calibre by Mentor Graphics or a similar tool. The influence of the two main parasitic capacitor types (those parallel to and those common to the capacitors in the arrays) on the DAC characteristics is analyzed. We provide expressions for fast manual calculation of the integral non-linearity (INL) and differential non-linearity (DNL) errors according to the values of the parasitic capacitors. Simulation results from a Verilog-A module based on this model are given. The model provides higher simulation speeds with accuracy close to that of a transistor-level model by using the extracted parasitic parameters.