Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs

This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band
k p
Hamiltonian within the nonequilibrium Green function formalism. Our model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the band structure. The effect of acoustic- and optical-phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in n-type InAs tunnel FETs induce a remarkable enhancement of I
_on
with a small degradation of the subthreshold slope, as well as large improvements in the I
_off
versus I
_on
tradeoff for low I
_off
and V
_DD
values. Hence, an important widening of the range of I
_off
and V
_DD
values where tunnel FETs can compete with strained silicon MOSFETs is obtained.