The RIVP image processor array

The authors present the radar video image processor (RIVP) architecture and its performance. RIVP is an SIMD (single instruction multiple data) linear processor array with 128 bit-serial processing elements (PEs) integrated on one chip. Each PE incorporates a serial-parallel multiplier and a bit-serial ALU with a 32-b accumulator register. The special multiplier-ALU-accumulator design makes convolutions, which is a basic image processing operation, very effective. Large IO and inter processor communication bandwidth is obtained by the use of four 32-b double-ported IO registers and a 16-b internal bidirectional shift register in each PE. Four RIVP chip and an internal micro controller are packaged n a 2" /spl times/ 2" multi chip module (MCM) and is a stand-alone 512 PE SIMD processor array. A 512 PE MCM module is suited for real-time video-input processing of 512 /spl times/ 512 images. Each RIVP MCM is capable of 1 Giga multiply-accumulations per second on 10 by 16 bit words at 50 MHz clock frequency. In some applications several RIVP MCM modules are needed. For instance, in the pulse Doppler radar example given eight modules are used to obtain a total of 4096 processing elements in series.