Impact of process variability on universal gates

The exponential growth in the ULSI technology is due to scaling but the certainity in the performance of chips is reducing in nano scale regime. The process variation is growing as a major concern and thus need to be analysed necessarily below sub micron regime. In this paper, the effect of process induced parameter variation on the delay of universal gate is analysed. Device variations fluctuations in MOS parameters viz. effective gate length (L
_eff
), threshold voltage (V
_th
), thickness of the gate oxide (t
_ox
), and the drain/source region parasitic resistance (R
_dsw
) are considered in this work. The analysis is done with Monte Carlo method using T-SPICE for various technologies. The comparisons of the results show that process variations become important in deep sub micron regime and increase the uncertainity in speed.