2-channel 2-layer inner-stack memory-module design for LPDDR2/3 DRAM

The LPDDR2 and the LPDDR3 are promising DRAMs for high-performance mobile sets on the beneficial of low power consumption and high operating speed. We designed these LPDDR2/3-based 2-channel ISM in 10mm × 10mm size with a 2-layer substrate using conventional design-rules and assembly processes by devising and applying several schemes such as location optimization of the ISM bond fingers and the test pads dependent on chip-mounting direction and routing scheme, selection of the unavoidable stubs by impact proportion, calculation logic for matrix, number, size, and pitch of the test pad considering maximal line numbers routable between adjacent test pads, solder-resist open size of the test pad in consideration of the test method and the real PiP structure, loop inductance matching by power/ground design, and so on The resultant LPDDR2 and LPDDR3 ISMs showed proper operation up to 1066Mbps and 1600Mbps, respectively. Also they showed almost the same performance at both the ISM bond finger and the test pad, which is very important both to maximize the test yield and to minimize the field failure in real product application. The schemes will be efficiently applicable to the design of cost-effective high-performance packages including the PoP and the interposers.