Challenges of electrostatic discharge (ESD) protection in silicon nanowire technology

Electrostatic discharge (ESD) induced failures continue to be a major reliability concern in the semiconductor industry. Such a concern will in fact be intensified as the CMOS technology is scaling toward the 22-nm and beyond. This paper covers the issues and challenges pertinent to the design of electrostatic discharge (ESD) protection solutions of modern and future integrated circuits, including the high-voltage, low-voltage, and emerging nanowire technologies.